The present invention relates to a nonvolatile memory in which overwrite is possible and a bipolar source circuit that can be ideally employed for memory overwrite.
While electrical batch deletion is possible in flash memory, it is necessary to batch delete data prior to a write even when the data are to be only partially overwritten, which, in turn, necessitates a full write operation for all the data.
In order to eliminate this inconvenience, the technology whereby memory cells are divided into blocks so that deletion by the block is made possible has been disclosed in "IEEE Journal of Solid State Circuits" Volume 29, Fourth Issue, April 1994, pages 454-459 (reference 1), in the technical report of IBICE. ICD 95.about.38 (1995.about.05) and in the Institute of Electronics, Information and Communication Engineers, Nos. 55.about.62 (reference 2).
While a nonvolatile memory which, as disclosed in references 1 and 2, is provided with a floating gate and writes and deletes data by employing an FN tunnel current and requires a high voltage for the FN tunnel, it requires only a small current. Therefore, internal voltages can be generated through an on-chip step-up circuit, achieving an advantage in that a flash memory, which enables an external single source voltage operation, can be easily manufactured.
However, since the FN tunnel phenomenon essentially takes place between two electrodes, when a memory cell array is constituted by taking advantage of this phenomenon, a problem of fluctuation in the threshold values (Vth) of unselected cells connected to a selected bit line, a selected word line or a selected P-well, i.e., disturbances in the threshold values, arises.
According to references 1 and 2, by setting the selected P.sub.-- well at -8V and setting all the selected word lines within a block at 10V, electrons are caused to be injected from the channels of the selected cells, i.e., all the cells connected to all the word lines within the selected block in this case, into the floating gate so that a data delete operation can be performed in units of blocks, as illustrated in FIG. 2(a). A voltage of -4V is applied from a common source and the channel potential is raised to -4V to ensure that the cells in an unselected block within a P-well are not disturbed by the -8V voltage in the same P-well, thereby preventing a P-well disturbance (see FIG. 2(b)).
In order to write data, as shown in FIG. 3(a), -8V is applied to the selected word lines, the block selection Tr (SG in the reference) is turned on at 8V, and 5V is applied to the drain of the selected cell by the main bit line (MBL) and electrons are drawn out from the floating gate. By setting the main bit lines of the cells from which no electrons are to be drawn out to 0V, it is possible to selectively write "1" and "0" in the data (see FIG. 3(b)).
In contrast, unselected blocks are protected from disturbance by turning off the block selection Tr (SG) at 0V to ensure that the 5V voltage at the main bit lines (MBL) does not exit to the sub bit lines, i.e., by achieving a floating state.
FIG. 1 shows an equalizing circuit for a memory cell array in the prior art. It is constituted of word lines WLn, each connected with a control gate that is capacitively coupled with a floating gate, main bit lines MBLn and a common source line SL.
Each main bit line is further connected with a sub bit line SBLn via a block selection transistor BST (indicated as SG in the references, which constitutes a block selection line BSL when connected in parallel to word lines).
However, this method presents a problem in that since a delete is performed in large units of a plurality of blocks (&gt;64 Kbytes according to the references), it is difficult to perform a delete in units of small sectors of 512 bytes each, as in a hard disk, necessitating much overhead in the system. To be more specific, while it is possible to perform a delete in units of word line sectors instead of in units of blocks by applying 10V only to, for instance, one word line instead of applying 10V to all the word lines within a selected block in a delete operation, it is difficult to assure a sufficient number of overwrite operations, since the disturbance becomes greater.
For instance, let us consider a situation in which a disturbance in the bit lines occurs during a write, with one block containing 64 word lines. In a block deletion, since bit line disturbances occur only while a write is performed once at each word line within the block after the deletion, even with an assured number of overwrite operations at 10,000, only 63 disturbances must be withstood. However, in order to assure the same number of overwrite operations in word line sector deletion, bit line disturbances 10,000 times greater than in block deletion, i.e. 63.times.10,000 must be withstood, making it difficult to assure a feasible number of overwrite operations for practical use.
Next, let us contemplate a P-well disturbance during a delete operation. In regard to the delete voltage in an FN tunnel-type flash memory, when the block selection line BSL, selected by applying, for instance, a positive 10V to the selected word line and applying, for instance -10V from the main bit line, is at 0V, the sub bit line selection transistor BST becomes turned on. This sets the sub bit line to -10V, and since the memory cell enters an on state at this point, a channel is formed, which sets the cell source to -10V as well as the cell drain. Because of this, if the source line is not divided into a main line and a sub line, all the sources and all the P-wells in the memory array are set to -10V. When the assured number of overwrites is 10,000, if the units of deletion are changed from blocks to word line sectors, the number of delete operations over which the P-well disturbance must be withstood increases from (the number of blocks in the same P-.sub.-- well.times.10,000) to (the number of blocks in the same P-well.times.63.times.10,000), which means that the service life is reduced to 1/63 what it would otherwise be. In order to improve on this, it may be possible to perform deletions with a shallower negative voltage applied to the P-wells and an increased positive voltage at the selected word lines. In that case, however, it becomes necessary for the transistors constituting the word line drive circuit to withstand a higher voltage, which, in turn, will present problems such as reduced drive capability because of the increased size of the X-decoder and an increase in the film thickness of the gate oxide film.
In particular, during a data write, since 5V is applied to the sub bit lines in a selected group and the unselected word lines within the selected group become grounded, the 5V potential between the grounded word lines and the sub bit lines causes a disturbance on the sub bit lines within the selected group.
As a means for preventing this sub bit line disturbance, a positive potential may be LR applied to unselected word lines within the selected group during a data write in order to reduce the difference in potential between the unselected word lines and the sub bit lines.
However, since the memory cells corresponding to the word lines supplied with the positive potential enter an on state, a current will flow to their source line, necessitating a large current for the write operation. In addition, if the source lines are made to float in order to prevent the current from flowing to them, the source line potential increases, inducing a new disturbance-related problems.